A conventional circuit design process usually starts with the synthesis of the HDL input files. Output of the synthesis step are Macro IBM VLSI Integrated Model (VIM) netlists for modeling the semiconductor fabrication of the circuit, DFTS/TLI (Design For Test Synthesis/Top Level Insertion) for adding testability features to the netlist, Chip-VIM netlist with test points for model the semiconductor fabrication of the circuit, etc. It may tale many days to process. Therefore, there is a need for a circuit design process that takes shorter period of time than the design process of the prior art.